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| CXP87800 CMOS 8-bit Single Chip Microcomputer Description The CXP87800 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP87852/87860. Piggyback/ evaluator type 100 pin PQFP (Ceramic) Features * A wide instruction set (213 instructions) which QFP supported cover various types of data. -- 16-bit operation/multiplication and division/ boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) * Applicable EPROM LCC type 27C512 (Maximum 60K bytes are available.) * Incorporated RAM capacity 2048 bytes * Peripheral functions -- A/D converter 8-bit, 12-channel, successive approximation method (Conversion time of 20s/16MHz) -- Serial interface Buffer RAM 1 channel (Auto transfer for 1 to 32 bytes) 8-bit and 8-stage FIFO 1 channel (Auto transfer for 1 to 8 bytes) Incorporated two-wire 8-bit and 8-stage FIFO 1 channel (Auto transfer for 1 to 8 bytes) -- Timer 8-bit timer, 8-bit timer/counter 19-bit time base timer, 32kHz timer/counter -- High precision timing pattern generator PPG 19-pin, 32-stage programmable RTG 5 pins, 2 channels -- PWM/DA gate output PWM output 12 bits, 2 channels (Repetitive frequency of 62.5kHz/16MHz) DA gate pulse output 13 bits, 4channels -- Servo input control Capstan FG, drum FG/PG, CTL input -- VSYNC separator -- FRC capture unit Incorporated 26-bit and 8-stage FIFO -- PWM output 14 bits -- VISS/VASS circuit Pulse duty auto detection circuit -- Remote control receiving circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO -- General purpose prescaler 7 bits (SYNC1 input frequency division, FRC capture possible.) -- HSYNC counter 12-bit event counter (SYNC1 input count) * Interruption 23 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP87800. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E96213-PS CXP87800 Pin Assignment in Piggyback Mode (QFP package) PI3/TO/DDO/ADJ PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 PI4/INT1/NMI VDD NC Vss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3/SDA1 PD2/SDA0 PD1/SCL1 PD0/SCL0 1 2 3 4 5 6 7 80 79 78 77 76 75 74 PI6/SO1 PI7/SI1 PE0/INT0/CKOUT PE1/EC/INT2/HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVss PF4/AN8 A12 A15 NC A14 VDD A13 TX TEX PI1/RMC PI2/PWM PI5/SCK1 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 9 10 11 12 13 14 15 16 17 18 19 20 21 4 A6 A5 A4 A3 A2 A1 A0 NC D0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE D7 D6 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND NC D1 D2 D3 D4 D5 22 A7 8 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. -2- PF7/AN11 PF6/AN10 PF5/AN9 EXTAL SCK0 XTAL RST SO0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CS0 Vss MP SI0 CXP87800 Pin Assignment in Evaluator Mode (QFP package) PI3/TO/DDO/ADJ PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 PI4/INT1/NMI VDD NC Vss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3/SDA1 PD2/SDA0 PD1/SCL1 PD0/SCL0 1 2 3 4 5 6 80 79 78 77 76 75 PI6/SO1 PI7/SI1 PE0/INT0/CKOUT PE1/EC/INT2/HCOUT PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVss PF4/AN8 TX TEX PI1/RMC PI2/PWM PI5/SCK1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A7/D7 7 8 9 10 A12 A15 4 11 12 13 14 15 16 17 18 19 20 21 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 NC RD 5 6 7 8 9 10 11 12 13 3 2 NC 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC HALT A10 E/P I/T MON 14 15 16 17 18 19 20 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SYNC GND RST WR NC C2 C1 22 A14 VDD A13 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. -3- PF7/AN11 PF6/AN10 PF5/AN9 EXTAL SCK0 XTAL RST SO0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CS0 Vss MP SI0 CXP87800 EPROM Read Timing (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Item Address data input delay time Address data hold time Symbol Pin A0 to A15 D0 to D7 A0 to A15 D0 to D7 0 Min. Max. 1001 752 Unit ns ns tACC tIH 1 At 12MHz operation (VDD = 4.5 to 5.5V) 2 At 16MHz operation (VDD = 4.5 to 5.5V) 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D7 Products List Products Option item Mask product CXP87852 Package ROM capacity Pull-up resistor for reset pin Input circuit format1 CXP87860 Piggyback/evaluator product CXP87800-U01Q 100-pin ceramic PQFP EPROM 60K bytes 27C512 x 1 Existent TTL schmitt 100-pin plastic QFP 52K bytes 60K bytes Existent/Non-existent CMOS schmitt/TTL schmitt 1 The input circuit format can be selected to PG4/SYNC0 and PG5/SYNC1, respectively. -4- CXP87800 Piggyback mode/evaluator mode can be switched as shown below. Evaluator mode Piggyback mode Piggyback/evaluator product Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU probe Note) Evaluation cap should be connected to CPU probe. -5- Package Outline Unit: mm 100PIN PQFP (CERAMIC) 18.7 16.3 0.2 81 81 PIN No. 1 INDEX 100 PIN NO. 1 INDEX INDEX 100 1 80 80 1 6.0 24.7 1.27 0.13 12.02 14.22 22.3 0.25 18.12 0.2 0.3 1.0 0.7 1.3 0.3 3.57 0.36 + 0.05 0.15 - 0.02 0.50 0.25 10.44 MAX -6- 51 51 50 50 0.45 9.48 11.66 15.58 0.2 SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L01 AQFP100-C-0000-A 30 30 31 31 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT CERAMIC GOLD PLATING 42 ALLOY 5.7g 0.3 0.08 0.65 0.05 4.5 CXP87800 |
Price & Availability of CXP87800
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